1. Field of the Invention
The present invention generally relates to dynamic random access memory devices, and more particularly, to an improvement for shortening time for a test of a dynamic random access memory device having a self-refresh function.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as a "DRAM") is widespread as a semiconductor memory suitable for high integration in a semiconductor substrate, since one memory cell is constituted of one switching transistor and one data storage capacitor. In a DRAM, it is necessary to carry out a "refresh operation" which periodically amplifies a data signal stored in a capacitor, since the data signal is retained by the capacitor. Most of DRAMs in recent years have a function (generally referred to a "self-refresh function") which may carry out a refresh operation without requiring internal or external refresh control. An example of a DRAM having a self-refresh function is disclosed in U.S. Pat. No. 4,933,907 issued to the same applicant as the present application.
FIG. 5 is a block diagram of a DRAM showing the background of the present invention. Referring to FIG. 5, a DRAM 100 includes a memory cell array 1 having 4,718,592 memory cells arranged in rows and columns, a row decoder 2 for selecting a word line in the memory cell array 1, a column decoder 3 for selecting a memory cell column to be accessed, an address buffer 4 for receiving an address signal externally applied in a time sharing manner, a sense refresh amplifier 5 connected to the memory cell array 1, and an IO gate circuit 6 for selectively connecting a bit line in the memory cell array 1 and an input buffer 7 and an output buffer 8. In FIG. 5, a line 100 also shows a semiconductor substrate.
A clock signal generator 9 generates various clock signals for controlling circuits in the DRAM 100 in response to an externally applied row address strobe signal /RAS and a column address strobe signal /CAS. A refresh control circuit 10 operates in response to a RAS and CAS system internal signal Sr applied from the clock signal generator 9, and generates a refresh control signal REF.
In the write operation, externally applied data signals DQ0 to DQ8 are applied to the 10 gate circuit 6 through the input buffer 7. The column decoder 3 selectively renders one switching circuit (not shown) in the IO gate circuit 6 conductive by decoding column address signals CA0 to CA8 applied through the address buffer 4. Therefore, a data signal is applied to a bit line (not shown) in the memory cell array 1. The row decoder 2 decodes row address signals RA0 to RA9 applied through the address buffer 4 to selectively activate one word line, not shown. Therefore, the data signal on the bit line is written to a memory cell (not shown) designated by the row decoder 2 and the column decoder 3.
In the read operation, a stored data signal is applied on a bit line (not shown) from a memory cell designated by the row decoder 2. The data signal on the bit line is amplified by the sense refresh amplifier 5. Since the column decoder 3 selectively renders one switching circuit (not shown) in the IO gate circuit 6 conductive, the amplified data signal is applied to the output buffer 8. Therefore, the data stored in the memory cell array 1 are provided outside through the output buffer 8.
FIG. 6 is a schematic diagram showing part of a conventional bit line peripheral circuit. FIG. 7 is a timing chart for explaining operations shown in FIG. 6. Description on the bit line peripheral circuit shown in FIG. 6 is given in Digest of Technical Papers of International Solid-State Circuits Conference held in 1985 (ISSCC85) pp. 252-253.
Referring to FIGS. 6 and 7, when a word line WLi is activated in the read operation, a switching transistor Qs of a memory cell MC is turned on. Therefore, a data signal stored in a capacitor Cs in the memory cell MC appears on a bit line BLj. Since the sense amplifier 5 constituted of transistors Q1 to Q4 is activated in response to activation control signals S.sub.P and S.sub.N, a subtle potential difference which appears between bit lines BLj and/BLj is amplified by the sense amplifier 5. Since a high level column selecting signal Yj is applied to the gates of transistors Q8 and Q9 from the column decoder 3, transistors Q8 and Q9 are turned on. Therefore, the data signal amplified by the sense amplifier 5 is applied to an IO line pair 6a, 6b. A data signal on the IO line pair 6a, 6b is transmitted to the output buffer 8.
Although the above description was given of the general read operation, it is pointed out that the similar operation is carried out in the refresh operation. However, since the high level column selecting signal Yj is not applied in the refresh operation, transistors Q8 and Q9 are not turned on. The data signal amplified by the sense amplifier 5 is applied again to the capacitor Cs through a conductive switching transistor Qs. In other words, although a signal electrical charge retained by the capacitor Cs is gradually reduced in accordance with time, the signal electrical charge is regained by periodical amplification and rewrite by the sense amplifier 5. The refresh operation in the DRAM is carried out in a detailed circuit in the above-described manner.
FIG. 8 is a circuit block diagram of a refresh control circuit 10 shown in FIG. 5. Referring to FIG. 8, the refresh control circuit 10 includes a CAS before RAS (hereinafter referred to as "CBR") refresh control circuit 11, and a self-refresh control circuit 12. A CBR refresh operation is carried out in response to a fall timing of externally applied signals /RAS and /CAS. In other words, the CBR refresh operation is carried out under external control. The CBR refresh control circuit 11 provides a refresh control signal REF for CBR refresh to the address buffer 4 in response to the RAS and CAS system internal signal Sr applied from the clock signal generator 9 shown in FIG. 5.
The self-refresh control circuit 12 includes an oscillating circuit 13 constituted of a ring oscillator, not shown, and a self-refresh cycle setting counter (hereinafter referred to as a "self-refresh counter") 14 for counting clock signals .phi.0 applied from the oscillating circuit 13. When the CBR refresh operation is not requested externally, a signal Ssr for requesting the self-refresh operation is automatically generated from the CBR refresh control circuit 11 to be provided to the self-refresh control circuit 12. The self-refresh counter 14 counts clock signals .phi.0 provided from the oscillating circuit 13 to apply the refresh control signal REF to the address buffer 4.
The oscillating circuit 13 starts oscillation in response to a self-refresh request signal Ssr, and provides clock signals .phi.0 having a cycle pulse of several .mu.s to ten and several .mu.s. The self-refresh counter 14 counts the clock signals .phi.0, and provides the refresh control signal REF including a cycle pulse of a hundred and several tens .mu.s.
A circulation cycle of the refresh control signal REF applied to the address buffer 4 in a self-refresh mode is set to as long a time length as possible within the range where a data signal stored in the memory cell is not lost. The reason is that it is necessary to make a refresh interval as long as possible to reduce the power consumption since the refresh operation involves activation of the sense amplifier. Therefore, taking into consideration data storage capability and power consumption of a DRAM, a ring oscillator having a long cycle is used in the oscillating circuit 13 provided in the self-refresh control circuit 12.
Generally, various tests are carried out before shipping products in semiconductor manufacturing factories. As for a DRAM, although various tests are carried out, it is pointed out that there are following problems particularly in a DRAM having a self-refresh function. As described above, since the oscillating circuit 13 provides a clock signal .phi.0 having a relatively long cycle, it takes long time to verify that the self-refresh function is normally carried out in the DRAM. In other words, in a self-refresh function verification test, it is verified that data signals stored in all memory cells continue to be retained properly by the self-refresh operation. Since the oscillating circuit 13 provides the clock signal .phi.0 of a relatively long cycle, the circulation cycle of the refresh control REF provided from the self-refresh counter 14 is also long. Therefore, it required long time for the row decoder 2 to designate all memory cell rows in accordance with the refresh control REF, whereby the entire time required for the self-refresh function verification test was increased.